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Research Paper | Electronics & Communication Engineering | India | Volume 5 Issue 4, April 2016
A Novel Design of Low Power 4:2 Compressor using Adiabatic Logic
Shaswat Singh Bhardwaj | Vishal Moyal [2]
Abstract: The purpose of the project is to design an adiabatic logic based low power 42 Compressor on the application of Two Phase Clocked Adiabatic Static Logic (2PASCL) technique, which shows the lowest power dissipation between different adiabatic logic families. It works on the principle of charge reversible logic. The present technique has smallest power dissipation relative to the standard CMOS design style by using different design specification such as different input signal switching frequency and supply voltage. The simulation is performed on S-edit of Tanner tool at 90nm BSIM4 technology.
Keywords: Adiabatic logic, Sinusoidal power supply, two phase power clock, energy recovery logic, 2PASCL technique, S-edit, Odd detector, compressor
Edition: Volume 5 Issue 4, April 2016,
Pages: 2433 - 2438
Similar Articles with Keyword 'Adiabatic logic'
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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015
Pages: 1409 - 1413Design and Analysis of Asynchronous 16*16 Adiabatic Vedic Multiplier Using ECRL and EEAL Logic
C. S. Harmya Sreeja | N. Sri Krishna Yadav
Downloads: 109
Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014
Pages: 2089 - 2092Low Power Security System by Using Dral
B. Rashika | R. Ramadoss