Low Power Security System by Using Dral
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 11, November 2014

Low Power Security System by Using Dral

B. Rashika, R. Ramadoss

Power dissipation in modern technologies is an important issue, and overheating is a serious concern for both manufacturer and customer. Everyday new technology which is faster, smaller and more complex is being developed.. This paper describes a side channel attack resistant coprocessor IC fabricated.The IC is being developed with both Reversible and Adiabatic logic and is been proposed with 180nm CMOS technology.. Reversible logic is used due to its less heat dissipating characteristics. Adiabatic logic (DRAL) is a design methodology for reversible logic in CMOS where the current flow through the circuit is controlled such that the energy dissipation due to switching and capacitor dissipation is minimized.It is capable of both forward encryption and reverse decryption by using AES algorithm for security applications. The Adiabatic logic with reversible technique is used and simulated in HSPICE. This technique is also used in allowing for efficient hardware reuse.

Keywords: Adiabatic logic, Reversible gates, AES algorithm, DPA, DRAL

Edition: Volume 3 Issue 11, November 2014

Pages: 2089 - 2092

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How to Cite this Article?

B. Rashika, R. Ramadoss, "Low Power Security System by Using Dral", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=OCT141385, Volume 3 Issue 11, November 2014, 2089 - 2092

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