Downloads: 101 | Views: 182
M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 3, March 2015
Analysis of Implicit Type Pulse Triggered Flip Flop
Richa Srivastav [4] | Dinesh Chandra [2] | Sumit Khandelwal
Abstract: In this paper, analysis of the pulse triggered flip flop is done. We compare the several styles of implicit type pulse triggered flip flop. In order to reduce the power consumption, conditional enhancement technique is used which speed-up the discharge path along the critical path. This was confirmed by simulation using 90nm technology, 1.0V power supply and clock frequency of 500MHz
Keywords: Low Power, Pulse Triggered, flip flop
Edition: Volume 4 Issue 3, March 2015,
Pages: 2158 - 2160