Design of 256 x 256 bit Vedic Multiplier

Aishwarya K M, Dr. Kiran V

Abstract: Multilplication has turned out to be an important operation in many DSP based applications and processors. The design for an area efficient, high speed and low power circuits are the prime objective for most of the VLSI circuits today. This paper presents a design for the implementation of 256 x 256 vedic multiplier. The design was carried out by designing the vedic multiplier for lower bits and by designing adders required for the design. The design was synthesized and delay was tabulated for varios vedic multipliers. The tool used in achieving this is Vivado.

Keywords: Urdhva Tiryagbhyam, Vedic mathematics, Vedic multiplier, Verilog

How to Cite?: Aishwarya K M, Dr. Kiran V, "Design of 256 x 256 bit Vedic Multiplier", Volume 10 Issue 9, September 2021, International Journal of Science and Research (IJSR), Pages: 122-125, https://www.ijsr.net/getabstract.php?paperid=SR21902110345, DOI: https://dx.doi.org/10.21275/SR21902110345