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Review Papers | Electronics & Communication Engineering | India | Volume 4 Issue 5, May 2015
Generation of a High Resolution Digital Pulse-Width Modulator through Digital Control in General Purpose Field Programmable Gate Array
K. Sohel Rana | Mhaske Kanchan Vikram
Abstract: Pulse width modulators are the basic building block in digital control architectures of any power converters. The design of power converters requires a high resolution high frequency pulse width modulators (HRPWMs) in order to reduce the size and cost, improved dynamic behaviour and power density. Hence, this paper proposes a review of digital pulse-width modulation (DPWM) architecture that takes advantage of the field programmable gate array (FPGA) advanced characteristics, especially the Internal Logic Blocks (Internal Carry Chain) present in the Virtex 4 FPGA and the Digital Clock Manager (DCM) present in the low cost Spartan - 3E FPGA. Given the interest of obtaining high-resolution DPWMs, a lot of different architectures have been proposed in the last years, and even a classification of them has appeared. These architectures are designed and compared to analyze the performance.
Keywords: DPWM, DCM Block, Delay line, Digital Control, Signal Resolution
Edition: Volume 4 Issue 5, May 2015,
Pages: 860 - 864
Similar Articles with Keyword 'Delay line'
Downloads: 101
M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015
Pages: 1180 - 1185A Fast-Locking All-Digital Deskew Buffer with DCC using Digital-Controlled Delay Line
A.Ashwini | H. Shravan Kumar
Downloads: 136
Research Paper, Electronics & Communication Engineering, India, Volume 6 Issue 6, June 2017
Pages: 860 - 864An Ultra-Low-Power Frequency Multiplier based on Mixed-Mode DLL with Output Frequency from 4 to 6 GHz
Priyadharshini M | Paul Richardson Gnanaraj J