International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Double Blind Reviewed

ISSN: 2319-7064



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Research Paper | Electronics & Communication Engineering | India | Volume 6 Issue 6, June 2017


An Ultra-Low-Power Frequency Multiplier based on Mixed-Mode DLL with Output Frequency from 4 to 6 GHz

Priyadharshini M | Paul Richardson Gnanaraj J


Abstract: An Ultra-Low-Power frequency multiplier based on Mixed-Mode DLL is presented in this paper. The operating frequency range is between 100 and 150 MHz which enables to produce output signals in the frequency range from 4 to 6 GHz. NAND-based delay cells are used in the digital part of the delay line due to their wide operating frequency range and small intrinsic delay. The analogue part of the delay line is based on the inverter delay chain with biasing circuit. It was added into the system to overcome the resolution problem and improve jitter performance. The total locking time changes from 10 to 14 clock cycles based on the operating frequency. The simulated peak-to-peak jitter is 21 ps and 1.95 ps for the generated clock operating at 5 GHZ and output clock of DLL operating at 125 MHz respectively.


Keywords: mixed-mode DLL, frequency generation, phase selection, jitter


Edition: Volume 6 Issue 6, June 2017,


Pages: 860 - 864


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How to Cite this Article?

Priyadharshini M, Paul Richardson Gnanaraj J, "An Ultra-Low-Power Frequency Multiplier based on Mixed-Mode DLL with Output Frequency from 4 to 6 GHz", International Journal of Science and Research (IJSR), Volume 6 Issue 6, June 2017, pp. 860-864, https://www.ijsr.net/get_abstract.php?paper_id=ART20174263



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