International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 113

Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 11, November 2015


Implementation of KL Algorithm for Partitioning using Perl

Swapnil D. Ninawe | Pranali D. Surkar


Abstract: This paper presents the implementation of KL algorithm for circuit partitioning using PERL. Circuit partitioning is NP hard problem. To solve the circuit partitioning problem, heuristic iterative algorithm is used. The algorithm treats the circuit as a graph, logic gates as nodes and interconnecting nets as edges. It randomly generates the initial partition of the circuit. The text file is used as an input which contains list of nodes and adjacency matrix of edges. The complete algorithm is implemented using arrays and associative arrays in PERL. Associative arrays are used to store the initial partition, improvement values, gain values and final partition. Nodes are stored as keys of associative arrays. The output file is generated which contains final partitions. This process helps to reduce the computation time of this iterative algorithm.


Keywords: Circuit partitioning, KL Algorithm, two-way partitions, improvement values, gain values, associative arrays and adjacency matrix


Edition: Volume 4 Issue 11, November 2015,


Pages: 1503 - 1506


How to Download this Article?

You Need to Register Your Email Address Before You Can Download the Article PDF


How to Cite this Article?

Swapnil D. Ninawe, Pranali D. Surkar, "Implementation of KL Algorithm for Partitioning using Perl", International Journal of Science and Research (IJSR), Volume 4 Issue 11, November 2015, pp. 1503-1506, https://www.ijsr.net/get_abstract.php?paper_id=NOV151439

Similar Articles with Keyword 'Circuit'

Downloads: 140 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 5, May 2013

Pages: 229 - 233

Study of R2R 4-Bit and 8-Bit DAC circuit using Multisim Technology

Raghavendra. R | S.A Hariprasad | M.Uttara Kumari

Share this Article

Downloads: 0

Research Paper, Electronics & Communication Engineering, India, Volume 11 Issue 5, May 2022

Pages: 1837 - 1841

Leakage Reduction Technique for Scan Flip-Flop

Nayini Bhavani | Rahul D [14] | Bhavani Kiranmai | J. Yeshwanth Reddy

Share this Article
Top