International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064




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Research Paper | Electronics & Communication Engineering | India | Volume 11 Issue 5, May 2022


Leakage Reduction Technique for Scan Flip-Flop

Nayini Bhavani | Rahul D [12] | Bhavani Kiranmai | J. Yeshwanth Reddy


Abstract: Scanning of test vectors during testing causes unnecessary and excessive switching in the combinational circuit compared to that in the normal mode of operation. In proposed system we have created a scan flip-flop based on MTcmos for leakage reduction which eliminates the power consumed due to unnecessary switching in the combinational circuit during scan shift, with a little impact on its performance. Multi-threshold CMOS (MTCMOS) power gating is a design technique in which a power gating transistor is connected between the logic transistors and either power or ground, thus creating a virtual supply rail or virtual ground rail, respectively, the new scan flip-flop by using sleep transistors it will reduce the leakage.


Keywords: Sequential circuit, MTCMOS, ATPG, CUT, Leakage current, scan flop


Edition: Volume 11 Issue 5, May 2022,


Pages: 1837 - 1841


How to Cite this Article?

Nayini Bhavani, Rahul D, Bhavani Kiranmai, J. Yeshwanth Reddy, "Leakage Reduction Technique for Scan Flip-Flop", International Journal of Science and Research (IJSR), Volume 11 Issue 5, May 2022, pp. 1837-1841, https://www.ijsr.net/get_abstract.php?paper_id=SR22512143826

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