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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015
Implementation of Enhanced Cache Controller with Multi-Sized Outputs
Sweety M Pinjani | Prof. V. B. Baru
Abstract: The major role of cache controller is reduction in the data transfer access time between the CPU and cache. The controller which is capable of handling a system with many cores is designed. It is also capable of giving multi-sized output like 1, 2, 4, 8 and 16 bytes. The operation of this controller is defined by 6 different states like Fetch Data, Read Cache, Write Cache, Read Memory, Write Memory and Give Data. The controller can be used for different ways of caches. The design is developed using Verilog HDL. A test bench is also developed to test the functionality of the design.
Keywords: Cache, cache controller, system performance, hit, miss
Edition: Volume 4 Issue 6, June 2015,
Pages: 2174 - 2176
Similar Articles with Keyword 'Cache'
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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015
Pages: 910 - 914Enhanced Way Tagged Cache Design Using Partial Tag Bloom Filter for Low Level (L2) Cache
Shaima Ibrahim | Sumi Babu
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Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015
Pages: 1760 - 1767Policy Based an Effective and Efficient Bandwidth Optimisation for Performance Enhancement of an Organisation
Ashok Kumar Tripathi [2] | Ramesh Bharti