Implementation of Enhanced Cache Controller with Multi-Sized Outputs
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 6, June 2015

Implementation of Enhanced Cache Controller with Multi-Sized Outputs

Sweety M Pinjani, Prof. V. B. Baru

The major role of cache controller is reduction in the data transfer access time between the CPU and cache. The controller which is capable of handling a system with many cores is designed. It is also capable of giving multi-sized output like 1, 2, 4, 8 and 16 bytes. The operation of this controller is defined by 6 different states like Fetch Data, Read Cache, Write Cache, Read Memory, Write Memory and Give Data. The controller can be used for different ways of caches. The design is developed using Verilog HDL. A test bench is also developed to test the functionality of the design.

Keywords: Cache, cache controller, system performance, hit, miss

Edition: Volume 4 Issue 6, June 2015

Pages: 2174 - 2176

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How to Cite this Article?

Sweety M Pinjani, Prof. V. B. Baru, "Implementation of Enhanced Cache Controller with Multi-Sized Outputs", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB155421, Volume 4 Issue 6, June 2015, 2174 - 2176

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