Enhanced Way Tagged Cache Design Using Partial Tag Bloom Filter for Low Level (L2) Cache
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



Downloads: 101

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 10, October 2015

Enhanced Way Tagged Cache Design Using Partial Tag Bloom Filter for Low Level (L2) Cache

Shaima Ibrahim, Sumi Babu

High-performance microprocessors utilize cache write-through policy for performance improvement, at the same time achieving good tolerance to soft errors in on-chip caches. Write-through policy also consumes large power due to the increased access to caches in different level during write operation. The objective of this paper is to improve the energy efficiency of write-through caches as well as improving the access time with a new cache architecture referred as way tagged cache. Many high performance microprocessor designs have chosen the write-through policy by maintaining the way tags of L2 cache in the L1 cache during read operations, proposed method uses L2 cache to work in an equivalent direct-mapping manner during write hits, which account for the majority of L2 cache accesses. During read operation, the way tag of the L2 cache information is available in L1 cache. In the proposed method, partial tag partially matches the incoming address with the cache line address. If the partial tag gives matches then full tag comparison will be performed. If no match is found, then the cache line (s) is not associated with the incoming address. Due to this the way-tag technique enables L2 cache to work in an equivalent direct mapping manner during write hits when the cache data compared with the input data, and it leads to reduce the significant energy without performance degradation and the access time. While the corresponding way tag information is not available in the way-tag arrays for read misses, therefore all the ways in the L2 cache are activated simultaneously under read misses.

Keywords: Multi level Cache, write-through policy, write- back policy

Edition: Volume 4 Issue 10, October 2015

Pages: 910 - 914

Share this Article

How to Cite this Article?

Shaima Ibrahim, Sumi Babu, "Enhanced Way Tagged Cache Design Using Partial Tag Bloom Filter for Low Level (L2) Cache", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=8101501, Volume 4 Issue 10, October 2015, 910 - 914

Enter Your Email Address




Similar Articles with Keyword 'Multi'

Downloads: 182

Informative Article, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 188 - 191

Realization of Smart City Using 5G Cognitive Radio

Lalit Chettri, Syed Sazad

Share this Article

Downloads: 152 | Monthly Hits: ⮙1

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 3, March 2015

Pages: 130 - 134

Segmentation of Touching Characters in Indian Scripts

B. Hari Kumar, N. Sateesh

Share this Article

Similar Articles with Keyword 'level'

Downloads: 127

Research Paper, Electronics & Communication Engineering, India, Volume 7 Issue 6, June 2018

Pages: 1662 - 1664

Enhancement of Gray Level Image by Fuzzy and Filter Technique

Monalisa Pandey, Pankaj Sharma

Share this Article

Downloads: 4 | Weekly Hits: ⮙1 | Monthly Hits: ⮙2

Review Papers, Electronics & Communication Engineering, India, Volume 10 Issue 5, May 2021

Pages: 195 - 198

Review - COVID-19 Detection System Using Image Processing and Biomedical

Prajkta D. Gawande, Dr. G. D. Dalvi

Share this Article

Similar Articles with Keyword 'Cache'

Downloads: 101

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1760 - 1767

Policy Based an Effective and Efficient Bandwidth Optimisation for Performance Enhancement of an Organisation

Ashok Kumar Tripathi, Ramesh Bharti

Share this Article

Downloads: 102

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2174 - 2176

Implementation of Enhanced Cache Controller with Multi-Sized Outputs

Sweety M Pinjani, Prof. V. B. Baru

Share this Article

Similar Articles with Keyword 'policy'

Downloads: 101

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1760 - 1767

Policy Based an Effective and Efficient Bandwidth Optimisation for Performance Enhancement of an Organisation

Ashok Kumar Tripathi, Ramesh Bharti

Share this Article

Downloads: 115

Survey Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2514 - 2516

A Review on Spectrum Sensing and Management under Wireless Cognitive Radio Networks

Arpita Saxena, Surbhi Kaushik

Share this Article

Similar Articles with Keyword 'write'

Downloads: 81

Research Paper, Electronics & Communication Engineering, India, Volume 9 Issue 10, October 2020

Pages: 1391 - 1397

Error Detecting Pen

Prateek Bansal, Ritvik Singhal

Share this Article

Downloads: 102

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2174 - 2176

Implementation of Enhanced Cache Controller with Multi-Sized Outputs

Sweety M Pinjani, Prof. V. B. Baru

Share this Article

Similar Articles with Keyword 'back'

Downloads: 93

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 3, March 2015

Pages: 508 - 513

Saliency Technique for Efficient Back Ground Subtraction

Aiswarya Muralidharan, S. Sivakumar

Share this Article

Downloads: 94

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 8, August 2014

Pages: 481 - 483

Communication of Multi Mobile-Robots Based On ZigBee Network

Taskeen Sultana, Zeenath

Share this Article



Top