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Research Paper | Electronics Communication Engineering | Volume 4 Issue 8, August 2015 | Pages: 329 - 332 | India
Low Power 1 bit Adiabatic SRAM Cell Design
Abstract: This paper presents the design of an Adiabatic static RAM with a bit line driver that reduces power dissipation by efficiently recovering energy from the bit capacitors in 180nm technology. Cadence simulations of a simple 1 bit Asymmetrical Adiabatic SRAM, that includes the energy recovering bit line drivers, and the sense amplifiers, show over 35 % of power savings at 1.8 V, in comparison with its conventional counterpart.
Keywords: SRAM Static Random Access Memory, Adiabatic circuitry, charge recovery low-energy design, low-power computing techniques
How to Cite?: Shobha Goutam, D. K. Mishra, "Low Power 1 bit Adiabatic SRAM Cell Design", Volume 4 Issue 8, August 2015, International Journal of Science and Research (IJSR), Pages: 329-332, https://www.ijsr.net/getabstract.php?paperid=SUB157266, DOI: https://dx.doi.org/10.21275/SUB157266