Domino CMOS Implementation of Power Optimized and High Performance CLA Adder

Kistipati Karthik Reddy, Jeeru Dinesh Reddy

Abstract: A carry look-ahead adder enhances speed of addition since it produces final carry out before generating final sum. Proposed work implements circuit design for a low-power high speed carry look ahead adder using Domino logic and results of propagation delay, average and maximum power is calculated in high precise analog design environment (ADE). The technology node assumed here is 180nm. Domino CMOS circuits enjoy area, delay and testability advantages over static circuits as such proposed architecture is general and can be upgraded to NP Domino or Zipper circuits. The basic building blocks starting at transistor level and logical blocks for adder and carry look-ahead logic is designed in Cadence Virtuoso cell-library and simulated in ADE_L.

Keywords: CMOS, ADE, CLA, LVS, DRC

How to Cite?: Kistipati Karthik Reddy, Jeeru Dinesh Reddy, "Domino CMOS Implementation of Power Optimized and High Performance CLA Adder ", Volume 4 Issue 5, May 2015, International Journal of Science and Research (IJSR), Pages: 1301-1305, https://www.ijsr.net/getabstract.php?paperid=SUB154455, DOI: https://dx.doi.org/10.21275/SUB154455