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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 5 Issue 4, April 2016
FPGA Implementation of Low Power and High Speed 64-Bit Multiply Accumulate Unit for Wireless Applications
R. Malleshwari | E. Srinivas [3]
Abstract: The MAC operation is the main computational kernel in Digital Signal Processing (DSP) architectures. The MAC unit is considered as one of the fundamental operations in DSP and it becomes a basic component in Application-Specific-Integrated-Circuits (ASIC). The MAC unit determines the speed of the overall system, it always lies in the critical path. Developing a high speed MAC is crucial for real time DSP applications. In this project 64-bit MAC unit is designed and it performs multiplication and addition to accumulator at a time in a summation network and here two architectures are developed, i. e. merged and proposed architechtures. The merged architecture is based on fully utilizing the summation tree. Feeding the accumulated data bits into the unused inputs of 42 compressors. This will save the cost of the additional accumulator by merging the accumulation operation with the multiplication circuit. In proposed 64-bit multiply and accumulate unit architecture, saving the area is achieved by fully utilizing the compressors instead of putting zeros in free inputs by using 52 compressor technique. And increasing the speed is achieved by reducing the critical path by changing the MAC structure. The proposed 64-bit MAC unit saves 21.9 % of area, 75.7 % of power and reduces the delay by 12 % compared to the regular merged 64-bit MAC unit.64-bit MAC unit is designed by using verilog HDL in Xilinx ISE14.3i and implemented on Zynq FPGA development board.
Keywords: Multiply accumulate unit MAC, digital signal processing, compressors, and 42compressor, 52compressor
Edition: Volume 5 Issue 4, April 2016,
Pages: 1462 - 1467