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Case Studies | Electronics & Communication Engineering | India | Volume 4 Issue 2, February 2015

A New Methodology for Error Detection and Correction to Realize Fault Tolerant Memory

Neethu V ^[5] | Anju S L

Abstract: Scaling of CMOS technology to nanoscale increases soft error rate in memory cells. Both single bit upset and Multiple Cell Upsets (MCUs) causes reliability issues in memory applications. Hence to provide fault-tolerant memory cells, Error Correction Codes (ECCs) are used. But these codes require more area, power and higher delay overhead. Thus Matrix Codes (MCs) based on Hamming codes and parity codes are used for detection and correction of multiple errors with less decoding delay. The use of matrix codes is capable of correcting only two errors. Hence to maximize the capability of error detection and correction, Decimal Matrix Code (DMC) based on decimal algorithm is used. This algorithm utilizes decimal integer addition and decimal integer subtraction to detect and correct errors. DMC uses encoder reuse technique for fault tolerant memory protection. The use of this algorithm enables more errors to be detected and corrected by the utilization of large number of redundant bits. Thus the framework can be modified so as to reduce the number of redundant bits by means of using parity matrix codes in which a 32 bit data is divided into 2bits of 16 blocks. Coding can be done by means of VHDL language and ModelSim can be used for simulation.

Keywords: Soft errors, decimal algorithm, syndrome, redundant bit, DMC encoder, DMC decoder

Edition: Volume 4 Issue 2, February 2015,

Pages: 1689 - 1694

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