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Review Papers | Electronics & Communication Engineering | India | Volume 3 Issue 9, September 2014
LDPC Minimum Sum Algorithm Decoder with Weight (3, 6) Regular Parity Check Matrix: A Review
Mamta Prakash [2] | Girraj Prasad Rathore [2]
Abstract: Low-Density parity-check (LDPC) codes are unit one in every of the foremost powerful error correcting codes obtainable nowadays. Their Shannon capability approaching performance and lower cryptography quality have created them the simplest choice for several wired and wireless applications. This paper offers a review on the one of the best technique for error detection and correction. The paper includes all the previous work related to the LDPC codes.
Keywords: LDPC, Decoder, Min-sum Algorithm, FPGA
Edition: Volume 3 Issue 9, September 2014,
Pages: 2033 - 2034
Similar Articles with Keyword 'LDPC'
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Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 3, March 2016
Pages: 2240 - 2243Implementation of Data Encoding Techniques for Reducing Area, Power Consumption in Network-on-Chip for LDPC Applications
Vijaykumar Jadhav | K. Sujata
Downloads: 105
Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 12, December 2015
Pages: 1451 - 1453Hardware Implementation of Min-Sum Decoder for Low Density Parity Check Codes
Mamta Prakash [2] | Girraj Prasad Rathore [2]