International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064




Downloads: 105

Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 12, December 2015


Hardware Implementation of Min-Sum Decoder for Low Density Parity Check Codes

Mamta Prakash [2] | Girraj Prasad Rathore [2]


Abstract: Low Density Parity Check (LDPC) technique is highly used in the communication protocol to effectively transfer data from transceiver end to receiver end. In this paper a highly efficient decoding technique viz. min-sum has used to transfer data. The data from the communication channel is used for the decoding process. Min-Sum algorithm decoder is implemented and simulation is done using Model sim. The hardware synthesis results are shown using Xilinx ISE 14.1 and Spartan 6 FPGA board.


Keywords: LDPC, Decoder, Min-sum Algorithm, FPGA


Edition: Volume 4 Issue 12, December 2015,


Pages: 1451 - 1453


How to Cite this Article?

Mamta Prakash, Girraj Prasad Rathore, "Hardware Implementation of Min-Sum Decoder for Low Density Parity Check Codes", International Journal of Science and Research (IJSR), Volume 4 Issue 12, December 2015, pp. 1451-1453, https://www.ijsr.net/get_abstract.php?paper_id=NOV152281

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