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Research Paper | Electronics & Communication Engineering | India | Volume 5 Issue 4, April 2016
Analysis of Different Power Efficient Flip-Flops
Savita Pandey | Padmini Sahu
Abstract: A power efficient flip flop dissipates very less power as compared to normal flip flops. In this paper different power efficient flip-flop switch different specific features are compared. A specified category of power efficient flip-flops known as the Dual Edge Triggered flip-flops are also considered in this comparison. The Dual Edge Triggered flip-flops responses to both positive and negative edge of clock. Hence this flip-flop can significantly reduce the clock related power. In this article, we compare several published implementations of power efficient flip-flops for performance & power consumption.
Keywords: Dual Edge Triggering, Conditional Capture Technique, Conditional Precharge, Power Delay Product, Clock Distribution Network
Edition: Volume 5 Issue 4, April 2016,
Pages: 91 - 94
Similar Articles with Keyword 'Power Delay Product'
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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 6 Issue 11, November 2017
Pages: 2142 - 2145Novel Design of Low Power Nonvolatile 10T1R SRAM Cell
Vani Tripathi | Bhawna Trivedi [2]
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Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014
Pages: 2933 - 2937Design and Analysis of Low Power High Speed Area Efficient Multipliers using Compressors on FPGA
Ch. Naga Srinivasa Rao | K. V. B. Chandra Sekhar Rao