Novel Design of Low Power Nonvolatile 10T1R SRAM Cell
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 6 Issue 11, November 2017

Novel Design of Low Power Nonvolatile 10T1R SRAM Cell

Vani Tripathi, Bhawna Trivedi

Power is a major issue in today's system on chip design at deep submicron. It is very important to control power dissipation in cache memories because 70 % of chip area is covered by memory in microprocessors. Various low power circuits are proposed in the past for volatile memories to alleviate the problem of power dissipation. However in today's era nonvolatile SRAMs (NVSRAMs) are being proposed to restore data along with faster access after power off operation. This paper proposes a nonvolatile Low power 10T1R SRAM cell. The proposed non volatile SRAM cell comprises a conventional 6T SRAM cell, memristor with 1 Transistor, USL technique comprising of 3 transistors, thus making a 10T-1R SRAM Cell. The proposed cell operates in three modes namely write, power off and restore. By simulating the proposed design, the power dissipation has reduced substantially. Experimental results shows that various parameters such as power, delay, power delay product and leakage current has also improved compared to the previous work. The work is done in cadence virtuoso tool at 45nm technology using GDPK045 library with supply voltage Vdd=1V

Keywords: NVSRAM, Upper Switch level, leakage current, power, delay

Edition: Volume 6 Issue 11, November 2017

Pages: 2142 - 2145

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Vani Tripathi, Bhawna Trivedi, "Novel Design of Low Power Nonvolatile 10T1R SRAM Cell", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=ART20178498, Volume 6 Issue 11, November 2017, 2142 - 2145

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