Rupali Dhobale, Kalyani Ghate, Nikhil Pimpalgaonkar, R. B. Khule
Abstract: Viterbi algorithm is employed in wireless communication to decode the Convolution codes; those codes are used in every robust digital communication systems. Such decoders are complex & dissipate large amount of power. Thus the paper presents the design of an Adaptive Viterbi Decoder (AVD) that uses survivor path with parameters for wireless communication in an attempt to reduce the power and cost and at the same time increase in speed. Most of the researches work to reduce power consumption, or work with high frequency for using the decoder in the modern applications such as 3 GPP, DVB, and wireless communications. Field Programmable Gate Array technology (FPGA) is considered a highly configurable option for implementing many sophisticated signal processing tasks. The proposed decoder design is simulated on ModelsimSE6.3f and implemented using VHDL code.
Keywords: Viterbi Algorithm, Adaptive Viterbi Decoder, Field Programmable Gate Array, VHDL, ASIC