Implementation of Adaptive Viterbi Decoder for Wireless Communication
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 3, March 2013

Implementation of Adaptive Viterbi Decoder for Wireless Communication

Rupali Dhobale, Kalyani Ghate, Nikhil Pimpalgaonkar, R. B. Khule

Viterbi algorithm is employed in wireless communication to decode the Convolution codes; those codes are used in every robust digital communication systems. Such decoders are complex & dissipate large amount of power. Thus the paper presents the design of an Adaptive Viterbi Decoder (AVD) that uses survivor path with parameters for wireless communication in an attempt to reduce the power and cost and at the same time increase in speed. Most of the researches work to reduce power consumption, or work with high frequency for using the decoder in the modern applications such as 3 GPP, DVB, and wireless communications. Field Programmable Gate Array technology (FPGA) is considered a highly configurable option for implementing many sophisticated signal processing tasks. The proposed decoder design is simulated on ModelsimSE6.3f and implemented using VHDL code.

Keywords: Viterbi Algorithm, Adaptive Viterbi Decoder, Field Programmable Gate Array, VHDL, ASIC

Edition: Volume 2 Issue 3, March 2013

Pages: 24 - 28

Share this Article

How to Cite this Article?

Rupali Dhobale, Kalyani Ghate, Nikhil Pimpalgaonkar, R. B. Khule, "Implementation of Adaptive Viterbi Decoder for Wireless Communication", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=IJSRON2013514, Volume 2 Issue 3, March 2013, 24 - 28

76 PDF Views | 55 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'Viterbi Algorithm'

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2184 - 2187

BER Analysis of Turbo Coded Channel

Dinesh Verma, Manish Kumar

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 3, March 2013

Pages: 24 - 28

Implementation of Adaptive Viterbi Decoder for Wireless Communication

Rupali Dhobale, Kalyani Ghate, Nikhil Pimpalgaonkar, R. B. Khule

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 773 - 777

Distributed Speech Recognition HMM Modelling

Gauri A. Deshpande, Pallavi S. Deshpande

Share this Article

Similar Articles with Keyword 'Field Programmable Gate Array'

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1862 - 1867

FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations

Lekshmipriya S., Suby Varghese

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2689 - 2691

VLSI Implementation of 2048 Point FFT

Zena Vatsa, Sumaya

Share this Article

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 1, January 2015

Pages: 1846 - 1848

A Review on Implementation of FPGA for Automatic Reverse Braking System

Divya Thakur, A. P. Thakare

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 1595 - 1597

Design and Implementation High Reliability PWM Modulator Using Triple Modular Redundancy with Spare Arrangement

Dikshant Khanke, Dr. P. B. Patil

Share this Article

Survey Paper, Electronics & Communication Engineering, India, Volume 5 Issue 5, May 2016

Pages: 1575 - 1578

A Survey on Partial Reconfiguration Techniques

Sowmya Aithal

Share this Article

Similar Articles with Keyword 'VHDL'

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 11, November 2016

Pages: 422 - 426

An Segmentation Under Connected Components Based on Watershed Algorithm Using FPGA Processor

R. Kiruthikaa, S. Salaiselvapathy

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 2 Issue 7, July 2013

Pages: 264 - 267

Implementation of an Arithmetic Logic Unit using Area Efficient Carry Look-Ahead Adder and Booth's Multiplier

Sarwagya Chaudhary

Share this Article

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 2195 - 2198

FFT with Minimum Hardware Utilization and Latency Using NEDA

Deepaa S S, Sheela Devi Aswathy Chandran

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 1, January 2016

Pages: 1057 - 1059

8 Bit Instructional Processor Performing ALU Operations using FPGA

Nikita V. Nandanwar, A. B. Diggikar

Share this Article

Research Paper, Electronics & Communication Engineering, Egypt, Volume 5 Issue 4, April 2016

Pages: 2089 - 2093

Design of Switched Resistor ?? ADC Using VHDL-AMS Tool

Ahmed Osman Hamaad, Mohyldin A. Abo-Elsoud, A. M. Abo-Talib

Share this Article

Similar Articles with Keyword 'ASIC'

Research Paper, Electronics & Communication Engineering, Vietnam, Volume 3 Issue 8, August 2014

Pages: 1541 - 1544

Design and Manufacture Electronic Scales for Adult Patients

Le Xuan Canh, Kien NguyenPhan, Hoang ChuDuc

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 992 - 995

ASIC Design of Sample Rate Convertor

Roopa M, H. Sudha

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 5, May 2014

Pages: 1772 - 1776

Comparative Study of the Sinusoidal Oscillator by using Current Conveyor

Gargi Sharma, Jagandeep Kaur, Neeraj Gupta

Share this Article

Comparative Studies, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 764 - 767

Design Low Power 10t and Comparison 16t, 14t and 11t Full Adder Using Invariant Parameter at 45nm Technology

Umashankar Dhepra, Rajkumar Gehlot

Share this Article

Research Paper, Electronics & Communication Engineering, Bangladesh, Volume 3 Issue 8, August 2014

Pages: 1017 - 1022

Simulink based Cooperative (Hard Decision Fusion) and Non-Cooperative Spectrum Sensing in Cognitive Radio Using Cyclostationary Detection

Niger Fatema, Ikram Ilyas, Dr. Md. Abdur Rahman

Share this Article
Top