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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014

A Novel Approach to 32-Bit Approximate Adder

Shalini Singh ^[5] | Ghanshyam Jangid ^[6]

Abstract: The probability of errors in the present VLSI technology is very high and it is increasing with technology scaling. Removing all errors is not required for certain applications and it is also a very expensive task. There are certain applications where the approximate result is acceptable e. g. image processing and video processing. For these applications Approximate Adder is proposed which provide approximate result at very high speed than the conventional adder. This error-tolerant adder is easy to develop the accuracy output and simultaneously achieves excellent improvement in both the area and speed performance. By comparing previous conventional counter parts and approximate adder the proposed approximate adder is to be attaining more than 20 % improvements in speed. One important potential application of the proposed adder in digital signal processing systems is that can tolerate certain amount of errors. The proposed adder provides improvement in delay and area at the same time at the cost of accuracy. Simulation result shows improvement in speed and area respectively over conventional adder.

Keywords: Adders, digital signal processing DSP, approximate adder, high-speed integrated circuits, VLSI

Edition: Volume 3 Issue 7, July 2014,

Pages: 240 - 244

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