Abstract: Design of 256 x 256 bit Vedic Multiplier
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Open Access | Fully Refereed | Peer Reviewed

ISSN: 2319-7064

Downloads: 1 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Student Project | Electronics & Communication Engineering | India | Volume 10 Issue 9, September 2021

Design of 256 x 256 bit Vedic Multiplier

Aishwarya K M, Dr. Kiran V

Multilplication has turned out to be an important operation in many DSP based applications and processors. The design for an area efficient, high speed and low power circuits are the prime objective for most of the VLSI circuits today. This paper presents a design for the implementation of 256 x 256 vedic multiplier. The design was carried out by designing the vedic multiplier for lower bits and by designing adders required for the design. The design was synthesized and delay was tabulated for varios vedic multipliers. The tool used in achieving this is Vivado.

Keywords: Urdhva Tiryagbhyam, Vedic mathematics, Vedic multiplier, Verilog

Edition: Volume 10 Issue 9, September 2021

Pages: 122 - 125

Share this Article

How to Cite this Article?

Aishwarya K M, Dr. Kiran V, "Design of 256 x 256 bit Vedic Multiplier", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SR21902110345, Volume 10 Issue 9, September 2021, 122 - 125

Enter Your Email Address


Similar Articles with Keyword 'Urdhva Tiryagbhyam'

Downloads: 114

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1321 - 1324

A Hierarchical Design of 32-bit Vedic Multiplier

Arpita S. Likhitkar, M. N. Thakare, S. R. Vaidya

Share this Article

Downloads: 130

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 12, December 2016

Pages: 239 - 242

Design and Implementation of 16 X 16 High speed Vedic multiplier using Brent Kung Adder

Nidhi Singh, Mohit Singh

Share this Article

Similar Articles with Keyword 'Vedic mathematics'

Downloads: 61

Masters Thesis, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020

Pages: 1042 - 1046

Renovated 32 Bit ALU Using Hybrid Techniques

Manju Davis, Uma N

Share this Article

Downloads: 103

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 3221 - 3230

Implementation of RSA Cryptosystem Using Ancient Indian Vedic Mathematics

Shahina M. Salim, Sonal A. Lakhotiya

Share this Article

Similar Articles with Keyword 'Vedic multiplier'

Downloads: 61

Masters Thesis, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020

Pages: 1042 - 1046

Renovated 32 Bit ALU Using Hybrid Techniques

Manju Davis, Uma N

Share this Article

Downloads: 105

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1843 - 1847

Design of 8 x 8 Vedic Multiplier using Quaternary-Logic & Pipelining Architecture

Vivek D. Wanjari, Prof. R. N. Mandavgane, Prof. Shailesh Sakhare

Share this Article

Similar Articles with Keyword 'Verilog'

Downloads: 121

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 3, March 2014

Pages: 108 - 112

Design and Simulation of Four Stage Pipelining Architecture Using the Verilog

Rakesh M. R

Share this Article

Downloads: 102

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2174 - 2176

Implementation of Enhanced Cache Controller with Multi-Sized Outputs

Sweety M Pinjani, Prof. V. B. Baru

Share this Article

Similar Articles with Keyword 'Urdhva'

Downloads: 61

Masters Thesis, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020

Pages: 1042 - 1046

Renovated 32 Bit ALU Using Hybrid Techniques

Manju Davis, Uma N

Share this Article

Downloads: 107 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1409 - 1413

Design and Analysis of Asynchronous 16*16 Adiabatic Vedic Multiplier Using ECRL and EEAL Logic

C. S. Harmya Sreeja, N. Sri Krishna Yadav

Share this Article

Similar Articles with Keyword 'Tiryagbhyam'

Downloads: 114

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1321 - 1324

A Hierarchical Design of 32-bit Vedic Multiplier

Arpita S. Likhitkar, M. N. Thakare, S. R. Vaidya

Share this Article

Downloads: 130

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 12, December 2016

Pages: 239 - 242

Design and Implementation of 16 X 16 High speed Vedic multiplier using Brent Kung Adder

Nidhi Singh, Mohit Singh

Share this Article

Similar Articles with Keyword 'Vedic'

Downloads: 61

Masters Thesis, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020

Pages: 1042 - 1046

Renovated 32 Bit ALU Using Hybrid Techniques

Manju Davis, Uma N

Share this Article

Downloads: 103

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 3221 - 3230

Implementation of RSA Cryptosystem Using Ancient Indian Vedic Mathematics

Shahina M. Salim, Sonal A. Lakhotiya

Share this Article

Similar Articles with Keyword 'mathematics'

Downloads: 61

Masters Thesis, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020

Pages: 1042 - 1046

Renovated 32 Bit ALU Using Hybrid Techniques

Manju Davis, Uma N

Share this Article

Downloads: 103

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 3221 - 3230

Implementation of RSA Cryptosystem Using Ancient Indian Vedic Mathematics

Shahina M. Salim, Sonal A. Lakhotiya

Share this Article

Similar Articles with Keyword 'multiplier'

Downloads: 1

Research Paper, Electronics & Communication Engineering, India, Volume 10 Issue 7, July 2021

Pages: 1498 - 1500

Design of Efficient Braun Multiplier for Arithmetic Applications

Telagamalla Gopi

Share this Article

Downloads: 61

Masters Thesis, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020

Pages: 1042 - 1046

Renovated 32 Bit ALU Using Hybrid Techniques

Manju Davis, Uma N

Share this Article
Top