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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014

A 64 Bit Pipeline Based Decimal Adder Using a New High Speed BCD Adder

Rahul Jain ^[3] | Khushboo Singh ^[2] | Ghanshyam Jangid ^[6]

Abstract: Binary arithmetic is one of the most primitive and most commonly used applications in microprocessors, digital signal processors etc. But binary arithmetic is unable to fulfill the requirement of fractional terms thus causing inexact results. And in commercial applications fractional terms are common and efficient output is must requirement so we use Binary Coded Decimal (BCD) adders. The conventional BCD adders are slow due to use of two binary adders. In this paper, we designed and implemented a new high speed BCD adder which use only one binary adder. The proposed BCD adder reduces the no. of binary adders due this reduction of adders the propagation delay of BCD adder is reduced. We also implemented 64 bit BCD adder using the pipelined technique. The proposed BCD adders are designed and implemented using verilog HDL in XILINX 9.2 version. The result of conventional BCD adders are compared with proposed BCD adders. the Experimental results demonstrate that the proposed BCD adders has 15.28 % faster than conventional BCD adder. the proposed 64 bit pipelined BCD adders is 55.39 % faster than conventional 64 bit BCD adder.

Keywords: Computer arithmetic, Decimal additions, VLSI design, Flagged binary adder, Correction circuit, pipeline, FPGA

Edition: Volume 3 Issue 7, July 2014,

Pages: 127 - 131

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