A 64 Bit Pipeline Based Decimal Adder Using a New High Speed BCD Adder
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014

A 64 Bit Pipeline Based Decimal Adder Using a New High Speed BCD Adder

Rahul Jain, Khushboo Singh, Ghanshyam Jangid

Binary arithmetic is one of the most primitive and most commonly used applications in microprocessors, digital signal processors etc. But binary arithmetic is unable to fulfill the requirement of fractional terms thus causing inexact results. And in commercial applications fractional terms are common and efficient output is must requirement so we use Binary Coded Decimal (BCD) adders. The conventional BCD adders are slow due to use of two binary adders. In this paper, we designed and implemented a new high speed BCD adder which use only one binary adder. The proposed BCD adder reduces the no. of binary adders due this reduction of adders the propagation delay of BCD adder is reduced. We also implemented 64 bit BCD adder using the pipelined technique. The proposed BCD adders are designed and implemented using verilog HDL in XILINX 9.2 version. The result of conventional BCD adders are compared with proposed BCD adders. the Experimental results demonstrate that the proposed BCD adders has 15.28 % faster than conventional BCD adder. the proposed 64 bit pipelined BCD adders is 55.39 % faster than conventional 64 bit BCD adder.

Keywords: Computer arithmetic, Decimal additions, VLSI design, Flagged binary adder, Correction circuit, pipeline, FPGA

Edition: Volume 3 Issue 7, July 2014

Pages: 127 - 131

Share this Article

How to Cite this Article?

Rahul Jain, Khushboo Singh, Ghanshyam Jangid, "A 64 Bit Pipeline Based Decimal Adder Using a New High Speed BCD Adder", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=2014883, Volume 3 Issue 7, July 2014, 127 - 131

108 PDF Views | 90 PDF Downloads

Download Article PDF



Similar Articles with Keyword 'Computer arithmetic'

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 127 - 131

A 64 Bit Pipeline Based Decimal Adder Using a New High Speed BCD Adder

Rahul Jain, Khushboo Singh, Ghanshyam Jangid

Share this Article

Survey Paper, Electronics & Communication Engineering, India, Volume 4 Issue 12, December 2015

Pages: 496 - 498

Improved Architectures for Fused Floating Point Add-Subtract Unit

Pooja Potdar, S. S. Tamboli

Share this Article

Similar Articles with Keyword 'VLSI design'

Survey Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 667 - 674

A Survey on VLSI Based Energy Conservation Techniques

Rakhi B. Menon, Gnana Sheela K

Share this Article

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1214 - 1218

Review on Different Types of Power Efficient Adiabatic Logics

Vijendra Pratap Singh, Dr. S.R.P Sinha

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 8, August 2015

Pages: 903 - 904

VLSI Design in Terms of Power System

Bhawana Singh, Nidhi Goyal

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1409 - 1413

Design and Analysis of Asynchronous 16*16 Adiabatic Vedic Multiplier Using ECRL and EEAL Logic

C. S. Harmya Sreeja, N. Sri Krishna Yadav

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 901 - 904

Low Power 8 Bit quantum ALU Implementation Using Reversible Logic Structure

Vijay G. Roy, P. R. Indurkar, D. M. Khatri

Share this Article

Similar Articles with Keyword 'pipeline'

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 3, March 2014

Pages: 108 - 112

Design and Simulation of Four Stage Pipelining Architecture Using the Verilog

Rakesh M. R

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014

Pages: 2202 - 2204

FPGA Implementation of Motion Feature Extraction Employing Pipelined Architecture

M. Nivethitha, B. Venkataramanaiah

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 5, May 2014

Pages: 671 - 674

A 1.8V 8-bit 100-MS/s Pipeline ADC in 0.18?m CMOS Technology

Bharti D.Chaudhari, Priyesh P. Gandhi

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 1730 - 1732

RTL Design and FPGA Implementation of Canny Edge Detector with Real Time Threshold Adjustment Capability

Lakshmamma K M, Chandana B.R

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 9, September 2015

Pages: 1332 - 1335

Low Power Self-Timed TCAM Based on Overlapped Search Mechanism with IP Filter Implementation

Jerrin Paul M, Hazel Elsa John

Share this Article

Similar Articles with Keyword 'FPGA'

Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 11, November 2016

Pages: 422 - 426

An Segmentation Under Connected Components Based on Watershed Algorithm Using FPGA Processor

R. Kiruthikaa, S. Salaiselvapathy

Share this Article

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1862 - 1867

FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations

Lekshmipriya S., Suby Varghese

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 878 - 884

ASIC Architectures for Implementing ECC Arithmetic over Finite Fields

Hemanth Ravindra, Jalaja S

Share this Article

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2835 - 2838

Efficient Implementation of Digital Receiver on FPGA

M. Sravani, B. Madhavi

Share this Article

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015

Pages: 2430 - 2432

Development of Low Cost Smart Antenna System and its FPGA Implementation

Harshveer Singh Grewal, Paramveer Singh Gill

Share this Article
Top