International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064

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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 7, July 2015

A Fast-Locking All-Digital Deskew Buffer with DCC using Digital-Controlled Delay Line

A.Ashwini | H. Shravan Kumar

Abstract: This paper presents a wide range fast lock all-digital deskew buffer using a digital controlled delay line, which achieves low jitter, fast lock, low power consumption and 50 % duty cycle correction. A cyclic time-to-digital converter is introduced to decrease the locking time in conventional register-controlled delay-locked loop. A balanced edge combiner to achieve 50 % output clock is also presented. A circuit is designed in 0.18m technology to demonstrate the feasibility of the proposed architecture with better figure of merit. The circuit can accept the input clock rates from 250 MHz to 1 GHz to generate close to output clocks with low jitter and phase noise. It owns the capability of closed loop power consumption.

Keywords: Delay-locked loop DLL, Digital-Controlled Delay Line DCDL, Duty Cycle Correction DCC, Edge Combiner, Time-to-Digital Converter TDC

Edition: Volume 4 Issue 7, July 2015,

Pages: 1180 - 1185

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