International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064

Downloads: 126 | Views: 168

M.Tech / M.E / PhD Thesis | Engineering Science | India | Volume 4 Issue 7, July 2015

Design of Inter-Integrated Circuit with BIST Method

Priyanka Lade | Sanjay Tembhurne

Abstract: The I2C (Inter-Integrated Circuit) Bus is a two-wire, low to medium speed, communication bus (a path for electronic signals) developed by Philips Semiconductors in the early 1980s. I2C was created to reduce the manufacturing costs of electronic products. The Inter-Integrated circuit protocol is used to attach two devices for communicating with each other in fast way excluding data losses. The I2C Bus is a time-proven, industry standard, communication protocol used in a wide variety of electronic products. I2C is found in products we use every day, like cellular and conventional telephones, computers, and ATMs (automatic teller machines). It slow cost and powerful features make I2C ideal for low to medium speed chip-to-chip communications. With the fast development of Integrated circuits (ICs) technology, the complication of the circuits has also increase day by day. To save time and money the circuit requires self -testability in hardware to palliate the product failure. BIST is system develop to performing functional testing at different speed. Built-in self-test (BIST) is a design technique that allows a circuit to test itself it is a set of structured test techniques for combinational and sequential logic, memories, multipliers and other embedded logic blocks. Built-in-self-test (BIST) is such a technique which can meet the necessity of self-testability with an effective solution over pricy circuit testing system. This synopsis proposed designing of Inter-Integrated Circuit (I2C) protocol with self-testing ability. In order to attain compact, stable and reliable data transmission, the I2C is designed with self-testability is needed.

Keywords: Inter-integrated Circuit, Built-in Self-test Architecture, Verilog HDL

Edition: Volume 4 Issue 7, July 2015,

Pages: 625 - 630

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