Design of an FFT Processor using Mixed-Radix Algorithm for OFDM system

Jaishri Katekhaye, Amit Lamba

Abstract: A parallel Fast Fourier Transform (FFT) processor for the use in Orthogonal Frequency Division Multiplexing (OFDM) is proposed here. The proposed processor is 64-point which is based on mixed radix (4-2) algorithm and execute 16-bit fixed point data format. The clock cycles required for the FFT processor are 92 which are less in number due to the use of parallel processing. The delay required for simulation of 64-point FFT is 11.924ns. For simulation we used XILINX 14.2 ISE software and for coding we employed Very High Speed Integrated Circuit Hardware Description Language (VHDL).

Keywords: FFT, Mixed Radix, OFDM, VHDL