Low Noise & High Speed Domino Logic Circuit

Reetu Narayan, Kumar Saurabh

Abstract: Dynamic logic style is used in high performance circuit designs due to its high speed. But during cascading of dynamic gates, problem arises due to charge sharing, charge redistribution and charge leakage. To avoid these problems, domino logic design is used in the circuit due to their advantages such as their high speed and less noise immunity. In this paper we have proposed a new domino circuit which has very small speed power product as compared to previous designs of domino logic circuits. Simulation are carried out for 90nm technology with Vdd = 1 Volt, for the case of OR gate.

Keywords: Domino logic, Dynamic Logic, Diode Footed Logic, Pull down Network, Pull up network, Charge sharing, charge leakage

How to Cite?: Reetu Narayan, Kumar Saurabh, "Low Noise & High Speed Domino Logic Circuit", Volume 4 Issue 6, June 2015, International Journal of Science and Research (IJSR), Pages: 3016-3021, https://www.ijsr.net/getabstract.php?paperid=SUB156004, DOI: https://dx.doi.org/10.21275/SUB156004