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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 5, May 2015

Design and Simulation of Low Dropout Regulator

Chaitra S Kumar | K Sujatha

Abstract: The proposed CMOS Low Dropout (LDO) regulator has been designed and simulated using TSMC 0.25 CMOS process in cadence analog design environment. This paper illustrates the design criteria and corresponding analysis relevant to LDO. The experimental result shows that, it regulates an output voltage at 3.3V from a 3.5V supply, with a minimum dropout voltage of 200mV at a maximum output current of 50mA using a reference voltage of 1.2V. The regulator provides a load regulation of 0.092V/A, line regulation of 0.16mV/V. Efficiency of 93.27 % is achieved. Detailed analysis of CMOS LDO has been presented.

Keywords: Low Drop-out, Low voltage regulator, CMOS, Linear regulator, power supply circuits, operational amplifier

Edition: Volume 4 Issue 5, May 2015,

Pages: 1404 - 1408