International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 126 | Views: 201

Review Papers | Electronics & Communication Engineering | India | Volume 4 Issue 4, April 2015


Implementation of Delay Measurement System for Small Delay Defect Detection

Supriya Thorat | Snehal Bhosale [3]


Abstract: Large scale integration of LSI has resulted in an increase in small delay defects. Small delay variations are induced by process variation, power supply noise as well as resistive opens and shorts. In this paper we use flip-flop design which is used in performing internal path-delay test and measurement using scan path technique. The proposed method measures delay of the explicitly sensitized paths using on chip variable clock generator. This method produces test patterns using Automatic Test Pattern Generator (ATPG).


Keywords: ATPG, Flip-flop, Measurement system, VLSI very large scale integration


Edition: Volume 4 Issue 4, April 2015,


Pages: 151 - 154


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