International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064




Downloads: 110 | Views: 207

Review Papers | Electronics & Communication Engineering | India | Volume 4 Issue 3, March 2015 | Rating: 6.6 / 10


Review on Floating Point Adder and Converter Units Using VHDL

Abhishek Kumar [16] | Mayur S. Dhait [2]


Abstract: Floating Point arithmetic is the most used way of approximating real number arithmetic for performing numerical calculations on modern computers. The advantage of floating-point representation is that it can support a much wider range of values rather than fixed point and integer representation. Addition/Subtraction, Multiplication and division are the common arithmetic operations in these computations. Among them floating point Addition is the most complex one. Adder is the core element of complex arithmetic circuits, in which input should be given in standard IEEE754 format. The main objective of the work is to design and implement a binary to IEEE 754 floating point converter for representing 32 bit single precision floating point values. Then the converter will be placed at the input side of the designed floating point adder module to improve the overall design. The modules are written using very high speed integrated circuit (VHSIC) Hardware Description Language (VHDL), and are then synthesized for Xilinx vertex E FPGA using Xilinx Integrated Software Environment (ISE) design suite 10.1.


Keywords: Floating point arithmetic, single precision, IEEE 754 format, VHDL, Xilinx


Edition: Volume 4 Issue 3, March 2015,


Pages: 1847 - 1851



How to Download this Article?

Type Your Valid Email Address below to Receive the Article PDF Link


Verification Code will appear in 2 Seconds ... Wait

Top