International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064

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Case Studies | Electronics & Communication Engineering | India | Volume 4 Issue 2, February 2015

FFT with Minimum Hardware Utilization and Latency Using NEDA

Deepaa S S | Sheela Devi Aswathy Chandran [2]

Abstract: New Distributed Arithmetic (NEDA) technique is being used in many digital signal processing systems that require MAC (multiply and accumulate) units. FFT (Fast Fourier Transform) is a method for computing the DFT with reduced number of computations. Distributed arithmetic technique is used to implement the sum of product terms and this technique uses ROM, Adder and Shifter for the purpose of implementation, but in NEDA technique only Adder and Shifter is used. So, the size of the architecture is reduced with respect to Distributed arithmetic technique, and thus the speed and throughput of the architecture is enhanced. The advantages of this method are reduced hardware and improved latency. The advantage of using Radix-4 algorithm is that it retains the simplicity of Radix-2 algorithm and gives the output with lesser complexity. Design of FFT using NEDA improves performance of the system in terms of speed, power and area. The VHDL language is used for coding, synthesis can be done by means of Xilinx-ISE and Model-Sim can be used for simulation.

Keywords: COrdinate Rotation DIgital Computer CORDIC, Distributed Arithmetic DA, Discrete Fourier Transform DFT, Fast Fourier Transform FFT, Multiply and Accumulate Unit MAC, New Distributed Arithmetic NEDA, Radix-4

Edition: Volume 4 Issue 2, February 2015,

Pages: 2195 - 2198

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