International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 114 | Views: 182

Case Studies | Electronics & Communication Engineering | India | Volume 4 Issue 2, February 2015 | Rating: 6.4 / 10


An Area Efficient Approach on PACC RLE Encoder

Ancy Mathew | Rafeekha M J


Abstract: Non volatile processor can retain its state when the power is off. Design challenge of non volatile processor is the excess area consumed by non volatile registers in it. Compared to regular CMOS flip flop, a ferro electric non volatile flip flop takes a large area due to its hybrid structure. Later Non volatile processor based on floating gate transistor was designed. But it also suffer from 40 percentage memory area overhead. Parallel Compare and Compress architecture is used to reduce the area of non volatile registers. The main block in PaCC architecture are PaCC encoder, PaCC decoder, Volatile registers, non volatile registers and non volatile flip flop controller. PaCC encoder is the work that is mainly focused. PaCC architecture uses Run length encoder (RLE), that compresses the data efficiently. Run length encoder is a simple form of data compression in which runs of data are stored as a single data value and count. This framework can be extended by replacing RLE encoder by Burrow wheeler transform and a comparative study on the area of both these encoders have to be done. The architecture was modeled using VHDL Coding and simulated using Modelsim.


Keywords: Run length encoder, parallel compare and compress encoder, nonvolatile flipflops, Xilinx ISE131, modelsim 63f


Edition: Volume 4 Issue 2, February 2015,


Pages: 1677 - 1680


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