Fault Tolerant Linear State Machine Design Approach for Safety Critical Systems Implemented on FPGA
Abstract: In this paper, a new method for the design of fault tolerant linear state machines with initial state 0 and one dimensional input and one-dimensional output is proposed. It is shown that the LFSR-implementation of the transfer function of a linear automaton can be utilized to correct transient errors in the memory elements. Since the state vector of a linear automaton is uniquely determined by the last n inputs and outputs, a transient error in a memory element can be corrected within n clock cycles by use of the corrected output symbols, where n is the number of components of the state vector
Keywords: TMR tripple modular redundancy, Voter logic
How to Cite?: Sunanda, Fathima Rehana, "Fault Tolerant Linear State Machine Design Approach for Safety Critical Systems Implemented on FPGA", Volume 4 Issue 2, February 2015, International Journal of Science and Research (IJSR), Pages: 1635-1636, https://www.ijsr.net/getabstract.php?paperid=SUB151574, DOI: https://dx.doi.org/10.21275/SUB151574