Power Reduction in Sub-Threshold Dual Mode Logic Circuits
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 117 | Views: 253

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 3, March 2015 | Popularity: 6.2 / 10


     

Power Reduction in Sub-Threshold Dual Mode Logic Circuits

Celine Elsa Jose, B Kousalya


Abstract: Power dissipation has always been a major concern in integrated circuit design. Even during static state, there is a small amount of leakage power. In this project we have implemented the Sub threshold Dual mode logic in CMOS basic gates and 2- bit Full Adder. This logic can bring down the total power. Hence a comparative analysis of power consumption is performed between conventional and Sub threshold dual modes. The logic has two modes of operation namely Static and Dynamic. In Static mode, there is a considerable decrease in the power consumed along with a moderate performance. Dynamic mode renders high performance compromising on an increase in power consumption. The power is evaluated using Tanner Simulation tool under 180nm technology.


Keywords: Complementary MOS, Dual Mode Logic DML, static power, dynamic power


Edition: Volume 4 Issue 3, March 2015


Pages: 572 - 575



Make Sure to Disable the Pop-Up Blocker of Web Browser


Text copied to Clipboard!
Celine Elsa Jose, B Kousalya, "Power Reduction in Sub-Threshold Dual Mode Logic Circuits", International Journal of Science and Research (IJSR), Volume 4 Issue 3, March 2015, pp. 572-575, https://www.ijsr.net/getabstract.php?paperid=SUB14964, DOI: https://www.doi.org/10.21275/SUB14964

Similar Articles

Downloads: 107

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015

Pages: 3321 - 3325

Comparative Study on Logic Gates Using Bulk Transmission Gate and Double Gate Transmission Gate

Sima Baidya, Arindam Chakraborty

Share this Article

Downloads: 107

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 11, November 2015

Pages: 2162 - 2166

A Review of Embedded Base Power Management Unit

Utsava Khare, Megha Gupta

Share this Article

Downloads: 108

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014

Pages: 2425 - 2430

Implementation of Core-Lock Mechanism as A Data Synchronization Method in Embedded Multi-Core Systems

Megha.S, Dr C R Byrareddy

Share this Article

Downloads: 108 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Research Proposals or Synopsis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 2277 - 2280

An Improved Feedthrough Logic for Low Power and High Speed Arithmetic Circuits

Avinash Singh, Dr. Subodh Wairya

Share this Article

Downloads: 109

Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015

Pages: 1214 - 1218

Review on Different Types of Power Efficient Adiabatic Logics

Vijendra Pratap Singh, Dr. S.R.P Sinha

Share this Article
Top