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M.Tech M.E PhD Thesis | Electronics Communication Engineering | Volume 4 Issue 3, March 2015 | Pages: 572 - 575 | India
Power Reduction in Sub-Threshold Dual Mode Logic Circuits
Abstract: Power dissipation has always been a major concern in integrated circuit design. Even during static state, there is a small amount of leakage power. In this project we have implemented the Sub threshold Dual mode logic in CMOS basic gates and 2- bit Full Adder. This logic can bring down the total power. Hence a comparative analysis of power consumption is performed between conventional and Sub threshold dual modes. The logic has two modes of operation namely Static and Dynamic. In Static mode, there is a considerable decrease in the power consumed along with a moderate performance. Dynamic mode renders high performance compromising on an increase in power consumption. The power is evaluated using Tanner Simulation tool under 180nm technology.
Keywords: Complementary MOS, Dual Mode Logic DML, static power, dynamic power
How to Cite?: Celine Elsa Jose, B Kousalya, "Power Reduction in Sub-Threshold Dual Mode Logic Circuits", Volume 4 Issue 3, March 2015, International Journal of Science and Research (IJSR), Pages: 572-575, https://www.ijsr.net/getabstract.php?paperid=SUB14964, DOI: https://dx.doi.org/10.21275/SUB14964