Leakage Power Reduction Techniques for Low Process Technology VLSI Design Circuits
Abstract: In VLSI based applications; specifications such as area, delay and power dissipation are taken in to account. In all the power dissipation plays important role. Power consumption reduces the battery life. In process technology is decreasing, in which the channel length is reduced leakage power increases. When the process technology is reducing leakage power becomes dominate. Leakage power is reduced considerably by using few techniques. We use LECTOR, LCNT and STACK ONOFIC techniques to reduce leakage power in VLSI design circuits such as inverter, NAND, NOR, MUX. For simulation EDA Tanner tool is used with 250nm technology.
Keywords: LECTOR, LCNT, PMOS, NMOS, Leakage power
How to Cite?: Kishor Kanaparthi, "Leakage Power Reduction Techniques for Low Process Technology VLSI Design Circuits", Volume 12 Issue 3, March 2023, International Journal of Science and Research (IJSR), Pages: 721-723, https://www.ijsr.net/getabstract.php?paperid=SR23313050557, DOI: https://dx.doi.org/10.21275/SR23313050557