International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


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Research Paper | Electronics & Communication Engineering | India | Volume 12 Issue 3, March 2023


Leakage Power Reduction Techniques for Low Process Technology VLSI Design Circuits

Kishor Kanaparthi [2]


Abstract: In VLSI based applications; specifications such as area, delay and power dissipation are taken in to account. In all the power dissipation plays important role. Power consumption reduces the battery life. In process technology is decreasing, in which the channel length is reduced leakage power increases. When the process technology is reducing leakage power becomes dominate. Leakage power is reduced considerably by using few techniques. We use LECTOR, LCNT and STACK ONOFIC techniques to reduce leakage power in VLSI design circuits such as inverter, NAND, NOR, MUX. For simulation EDA Tanner tool is used with 250nm technology.


Keywords: LECTOR, LCNT, PMOS, NMOS, Leakage power


Edition: Volume 12 Issue 3, March 2023,


Pages: 721 - 723


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