Leakage Power Reduction Techniques for Low Process Technology VLSI Design Circuits
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 3 | Views: 198 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Research Paper | Electronics & Communication Engineering | India | Volume 12 Issue 3, March 2023 | Popularity: 4.6 / 10


     

Leakage Power Reduction Techniques for Low Process Technology VLSI Design Circuits

Kishor Kanaparthi


Abstract: In VLSI based applications; specifications such as area, delay and power dissipation are taken in to account. In all the power dissipation plays important role. Power consumption reduces the battery life. In process technology is decreasing, in which the channel length is reduced leakage power increases. When the process technology is reducing leakage power becomes dominate. Leakage power is reduced considerably by using few techniques. We use LECTOR, LCNT and STACK ONOFIC techniques to reduce leakage power in VLSI design circuits such as inverter, NAND, NOR, MUX. For simulation EDA Tanner tool is used with 250nm technology.


Keywords: LECTOR, LCNT, PMOS, NMOS, Leakage power


Edition: Volume 12 Issue 3, March 2023


Pages: 721 - 723


DOI: https://www.doi.org/10.21275/SR23313050557



Make Sure to Disable the Pop-Up Blocker of Web Browser


Text copied to Clipboard!
Kishor Kanaparthi, "Leakage Power Reduction Techniques for Low Process Technology VLSI Design Circuits", International Journal of Science and Research (IJSR), Volume 12 Issue 3, March 2023, pp. 721-723, https://www.ijsr.net/getabstract.php?paperid=SR23313050557, DOI: https://www.doi.org/10.21275/SR23313050557

Similar Articles

Downloads: 2 | Weekly Hits: ⮙2 | Monthly Hits: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 13 Issue 8, August 2024

Pages: 1821 - 1823

Power Efficient Voltage Level Shifter using RCC Network and Stacking Technique

Rentala Laxmi Sindhuja

Share this Article

Downloads: 3 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Research Paper, Electronics & Communication Engineering, India, Volume 12 Issue 3, March 2023

Pages: 79 - 81

Design of Low Power Logic Gates for VLSI Design Circuits

Telagamalla Gopi

Share this Article

Downloads: 3 | Weekly Hits: ⮙2 | Monthly Hits: ⮙2

Research Paper, Electronics & Communication Engineering, India, Volume 12 Issue 3, March 2023

Pages: 470 - 472

Reduction of Leakage Power for VLSI Design Logic Gate Circuits

Kiran Renukuntla

Share this Article

Downloads: 101

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 8, August 2015

Pages: 1597 - 1602

Design Of 7T SRAM Cell Using Self-Controllable Voltage Level Circuit to Achieve Low Power

Vema Vishnu Priya, G.Ramesh

Share this Article

Downloads: 106

Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 7, July 2014

Pages: 1104 - 1108

Power Reduction Approach in Combinational Circuit (Half and Full Subtractor)

Navendra Rawat, Rakesh Jain

Share this Article
Top