Interfacing BLE Module on FPGA using Nios II
Abstract: This paper presents the implementation of Bluetooth Low Energy (BLE) on Field Programmable Gate Array (FPGA) using System on Programmable chip (SOPC). The design is implemented using the soft intellectual property (IPs) of the Nios II processor. The test results are verified on the serial terminal. This implementation has applications in the designing of wireless gateway on FPGA.
Keywords: Nios II Processor, BLE, UART
How to Cite?: Shama. S. Naik, Pritam Thomke, "Interfacing BLE Module on FPGA using Nios II", Volume 10 Issue 8, August 2021, International Journal of Science and Research (IJSR), Pages: 1020-1022, https://www.ijsr.net/getabstract.php?paperid=SR21817232729, DOI: https://dx.doi.org/10.21275/SR21817232729