Design of Two Stage CMOS Operational Amplifier

Rahul Kumar

Abstract: This paper presents a design of two stage CMOS operational amplifier, which operates at +1.8V and -1.8V power supply using 180nm CMOS technology. The op-amp designed is a two stage CMOS op-amp. The op-amp is designed to exhibit a gain bandwidth of 30 MHz and exhibits a gain of 68.74dB with a 179.94 phase margin. Design and simulation has been carried out in LTSPICE tool.

Keywords: CMOS op-amp design, frequency response, noise, simulation