Design of Two Stage CMOS Operational Amplifier
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 7 | Views: 504 | Weekly Hits: ⮙2 | Monthly Hits: ⮙3

Research Paper | Electronics & Communication Engineering | India | Volume 10 Issue 6, June 2021 | Popularity: 4.9 / 10


     

Design of Two Stage CMOS Operational Amplifier

Rahul Kumar


Abstract: This paper presents a design of two stage CMOS operational amplifier, which operates at +1.8V and -1.8V power supply using 180nm CMOS technology. The op-amp designed is a two stage CMOS op-amp. The op-amp is designed to exhibit a gain bandwidth of 30 MHz and exhibits a gain of 68.74dB with a 179.94 phase margin. Design and simulation has been carried out in LTSPICE tool.


Keywords: CMOS op-amp design, frequency response, noise, simulation


Edition: Volume 10 Issue 6, June 2021


Pages: 1505 - 1508


DOI: https://www.doi.org/10.21275/SR21622171146


Please Disable the Pop-Up Blocker of Web Browser

Verification Code will appear in 2 Seconds ... Wait



Text copied to Clipboard!
Rahul Kumar, "Design of Two Stage CMOS Operational Amplifier", International Journal of Science and Research (IJSR), Volume 10 Issue 6, June 2021, pp. 1505-1508, https://www.ijsr.net/getabstract.php?paperid=SR21622171146, DOI: https://www.doi.org/10.21275/SR21622171146

Top