Downloads: 49
Research Paper | Electronics Communication Engineering | Volume 10 Issue 6, June 2021 | Pages: 1505 - 1508 | India
Design of Two Stage CMOS Operational Amplifier
Abstract: This paper presents a design of two stage CMOS operational amplifier, which operates at +1.8V and -1.8V power supply using 180nm CMOS technology. The op-amp designed is a two stage CMOS op-amp. The op-amp is designed to exhibit a gain bandwidth of 30 MHz and exhibits a gain of 68.74dB with a 179.94 phase margin. Design and simulation has been carried out in LTSPICE tool.
Keywords: CMOS op-amp design, frequency response, noise, simulation
How to Cite?: Rahul Kumar, "Design of Two Stage CMOS Operational Amplifier", Volume 10 Issue 6, June 2021, International Journal of Science and Research (IJSR), Pages: 1505-1508, https://www.ijsr.net/getabstract.php?paperid=SR21622171146, DOI: https://dx.doi.org/10.21275/SR21622171146