Advanced Testing Frameworks for Next - Generation Semiconductor Devices Using Machine Learning

Botlagunta Preethish Nandan

Abstract: Semiconductor devices are the essential building blocks in today?s information technology and society. Next - generation semiconductor devices such as FinFETs, GAA - FETs, and nanowires have been proposed to serve for high - performance and low - power applications in the deep - submicron technology nodes. However, with the rapid scaling of semiconductor technology nodes, traditional test generation methods face large runtime and memory footprint challenges to ensure efficient fault diagnosis and reliability screening. In this regard, machine learning (ML) has emerged as a new paradigm to address the above issues with great success. This paper presents recent advanced testing frameworks for next - generation semiconductor devices by enabling ML. Several successful demonstrations are covered, creating and exploiting novel ML models of various levels of complexities. At the device level, fast test generation methods using shallow ML models are presented, yielding significant improvement in runtime and memory efficiency compared to existing commercial tools. At the circuit level, the applicability of deep learning - based approaches for stuck - at fault identification and location is explored. Finally, a massive data generation and representation learning framework for deep neural network - based built - in self - test (BIST) generation is presented to improve the design robustness of the built - in test (BIT) architectures for large - scale applications. The basic concepts and implementations are first introduced, followed by successful demonstrations and industrial applications. This opens up questions on how advanced ML models can improve existing approaches, where they might fail, and how to mitigate the biases. Manual test development for semiconductor chips relies on designers? knowledge, experience & heuristics, requiring substantial time & effort. ML models representative of test - influencing factors and their likely trade - offs can be created directly from the available test data. Such auto - generated ML models can then be exploited for test generation or validation, or to estimate the test cost based on semiconductor models. A bottleneck in this approach is the time - consuming, complex, intensive operation of taking different process steps to generate quality physical or logical test data on the specific test chips. ML methods are exceptionally data - hungry, requiring a large volume to train and generalize successfully. However, there are many untapped sources of ample simulation data both from older chips and different fabrication processes. It is possible to create new problem representations, or simulation domains, that standardize/normalize all factors not relevant to a particular problem. Various progressive domain adaptation methods can then be used to adapt existing ML models from these pre - trained representations to the new problem domain. Once adapted, the production ML models can be used for fully automated test generation or engineering studies.

Keywords: machine learning in testing, semiconductor device reliability, automated test generation, deep neural networks, domain adaptation strategies

How to Cite?: Botlagunta Preethish Nandan, "Advanced Testing Frameworks for Next - Generation Semiconductor Devices Using Machine Learning", Volume 9 Issue 12, December 2020, International Journal of Science and Research (IJSR), Pages: 1911-1920, https://www.ijsr.net/getabstract.php?paperid=SR20125160704, DOI: https://dx.doi.org/10.21275/SR20125160704