International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064

Downloads: 116 | Views: 212

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 9, September 2014

Implementation of Efficient Architecture for Vulnarability Packet Detection Using Verilog

M. Sivaramprasad | D. Sridhar [2]

Abstract: Network security has always been an important issue and its application is ready to perform powerful pattern matching to protect against virus attacks, spam and Trojan horses. However, attacks such as spam, spyware, worms, viruses, and phishing target the application layer rather than the network layer. Therefore, traditional firewalls no longer provide enough protection. However, the solutions in the literature for firewalls are not scalable, and they do not address the difficulty of an antivirus. The goal is to provide a systematic virus detection hardware solution for network security for embedded systems. Instead of placing entire matching patterns on a chip, our solution is based on an antivirus processor that works as much of the filtering information as possible onto a chip. The infrequently accessing off-chip data to make the matching mechanism scalable to large pattern sets. In the first stage, the filtering engine can filter out more than93.1 % of data as safe, using a merged shift table. Only 6.9 % or less of potentially unsafe data must be precisely checked in the second stage by the exact-matching engine from off-chip memory. This gives a high efficiency, improved performance and high ability of packet detection with less contribution of time in an effective way

Keywords: Algorithmic Attacks Embedded System, Memory Gap, Network Security, and Virus Detection

Edition: Volume 3 Issue 9, September 2014,

Pages: 2264 - 2270

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