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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 11, November 2014

Implementation of 100BASE-T4 Network Repeater Using FPGA

Sudarshan M. Dighade | Pranav P. Kulkarni

Abstract: Embedded systems have, in the main, been designed around microcontrollers. But increasing demand for develop performance, efficient signal processing and parallel processing means FPGAs are pass more closely to the heart of the embedded systems. This paper presents the idea of 8 port 100BASE-T4 fast Ethernet repeater design targeting its FPGA implementation is proposed which supports 100Mb/s over low grade category 3 UTP. The total estimated power consumption for proposed design has 335mW after the post placement and routing on Xilinx xc3s400 device. FPGA implementation has various advantage of altering the function of the platform to perform several tasks. The implementation results show the minimum power consumption which reduce drastically compared to that of reported design.

Keywords: FPGA, CRS, SFD, UTP

Edition: Volume 3 Issue 11, November 2014,

Pages: 909 - 913