Razor Based Low-Power Multiplier with Variable Latency Design

Sagar Latti, T C Thanuja

Abstract: Digital multipliers are the most critical part of the digital systems. The overall performance of the Digital system depends on the speed of the multipliers. Due to Aging effects like negative bias temperature instability in pMOS transistor when it is under negative bias, increases the threshold voltage of the transistor hence the speed of the multiplier reduces, a similar positive bias temperature instability effect occurs in nMOS transistor, when it is under positive bias. Hence it is required to design a reliable low power high performance multiplier. In this paper we propose a Razor based low power multiplier with variable latency design. In this multiplier the performance degradation due to the aging effect can be minimized using Adaptive Hold Logic. This logic is applied to column and row bypassing multipliers.

Keywords: Hold Logic, Column bypassing multiplier, Razor flip-flop, Row bypassing multiplier, Variable latency design