International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064

Downloads: 128 | Views: 200

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 5 Issue 1, January 2016

Implementation of Error Detection Network in High- Speed Variable Latency Speculative Han-Carlson Adder

C. Dhanalakshmi | C. Manjula [3]

Abstract: Variable latency adders have been recently proposed in literature. In variable latency adder unwanted interconnections also reduced compared with kogge-stone topology. Kogge-Stone adder consists of large number of black cells and many wire tracks. A variable latency adder employs speculation the exact arithmetic function is replaced with an approximated one that is faster and gives the correct result most of the time, but not always. In order to detecting the error, error detection network also used. The approximated adder is augmented with an error detection network that asserts an error signal when speculation fails. Speculative variable latency adders to reduce average delay compared to traditional architectures. This paper proposes a novel variable latency speculative adder based on Han-Carlson parallel- prefix topology which proposes the error detection network that reduces error probability compared to previous approaches. Several variable latency speculative adders, for various operand lengths, using both Han-Carlson and Kogge-Stone topology, have been synthesized using Xilinx 14.3. Obtained results show that proposed variable latency Han-Carlson adder used in high-speed application.

Keywords: Addition, digital arithmetic, parallel-prefix adders, speculative adders, speculative functional units, variable latency adders

Edition: Volume 5 Issue 1, January 2016,

Pages: 751 - 755

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