Low Power 16-Point FFT Processor Using Radix 2&4 Butterfly Units

Deekshitha K N, Divya Lakshmi M, Keerthana B K, Jalaja S

Abstract: This paper presents the implementation of a low power 16-point FFT processor utilizing a mixed radix approach. The design includes sub modules like twiddle multiplication, stage wise computation, butterfly computations. The main objective relies on the 16-point FFT, achieved by integrating the radix 2/4/2 algorithm (mixed radix) techniques along with low power strategies such as clock gating, FSM grey encoding and additional methods such as RAM memory. Likewise, we focus on obtaining the low power consumption. This approach results in a reasonable balance between power consumption and computational efficiency. The design process is conducted using Vivado and Cadence for simulation and synthesis to enhance power analysis reports. Overall, the dynamic power obtained using mixed approach is quiet high while, the best low power consumption was obtained after implementing FSM grey encoding. After optimization the dynamic power contribution is reduced to 14.60% of the total power consumption. This marks our approach to be effective for reducing the power consumption to 30.27%, significantly.

Keywords: low power FFT processor, mixed radix FFT, clock gating techniques, FSM grey encoding, power optimization in VLSI

How to Cite?: Deekshitha K N, Divya Lakshmi M, Keerthana B K, Jalaja S, "Low Power 16-Point FFT Processor Using Radix 2&4 Butterfly Units", Volume 15 Issue 1, January 2026, International Journal of Science and Research (IJSR), Pages: 149-153, https://www.ijsr.net/getabstract.php?paperid=MR26101175225, DOI: https://dx.doi.org/10.21275/MR26101175225