International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064

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Survey Paper | Electronics & Communication Engineering | India | Volume 2 Issue 4, April 2013 | Rating: 6.2 / 10


A Survey of HDLC Controllers

S. D. Samudra | S. P. Gaikwad [2]


Abstract: HDLC is an efficient protocol defined in the layer 2 of OSI model. HDLC is a group of protocols for transmitting synchronous data over a point-to-point link. Many chips have been designed for HDLC controllers. Not all the features of the controller are always needed. Due to the advantages of FPGA, controller chips are being designed according to the needs of system. This paper discusses the design and implementation of some such HDLC controllers.


Keywords: HDLC controller, FPGA, CRC, customization


Edition: Volume 2 Issue 4, April 2013,


Pages: 218 - 220


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