Design of Low Power 10T SRAM Cell with MTCMOS Technique

B. Sunanda, K. Nagendra Kumar

Abstract: Now-a-days Power consumption (or) power dissipation has becomes the most important criteria for implementing anyone of the circuit. While calculating the efficient value of the output of that particular circuit, we may use the concept of scaling. But, while increasing the scaling process there may be a loss of leakage current. Due to the leakage current the usage of power (power dissipation) is increased. For removing these kinds of leakage currents we are going to use power gating techniques. By using the power gating technique we can provide better power efficiency also. In this paper we are going to analyze the circuits using MTCMOS of power gated circuits with the help of low power VLSI design technique compare with other power gating techniques. The entire procedure may implement and simulated using Micro-wind Layout Editor & D. Sch (Digital Schematic).

Keywords: Power gating circuits, 10T SRAM, sleep methods

How to Cite?: B. Sunanda, K. Nagendra Kumar, "Design of Low Power 10T SRAM Cell with MTCMOS Technique", Volume 8 Issue 11, November 2019, International Journal of Science and Research (IJSR), Pages: 1028-1032, https://www.ijsr.net/getabstract.php?paperid=ART20202764, DOI: https://dx.doi.org/10.21275/ART20202764