Implementation of High Speed Flash ADC Using Multiplexer with Reduced Number of Preamplifier and Comparator Count

Rana Vikram Pratap Singh Yadav, Neelam Srivastava

Abstract: A high speed Flash analog-to-digital converter (ADC) using multiplexer with reduced number of preamplifiers and comparators is introduced. A conventional N-bit flash ADC requires 2N-1 preamplifiers and comparators while The high speed flash ADC only needs 2 (N-3)) +2 preamplifiers and 2 (N-2) +1 comparators. For a 6-bit resolution, the high speed flash ADC requires a reduce number of preamplifiers and comparator, compare with those of the conventional flash ADC. The high speed flash 6-bit ADC consists of a reference ladder network, track and hold circuit, 10 preamplifiers, 17 comparators, a (2x1) -MUX, 8 (4x1) -MUXs and logic gates for encoder and registers. The high speed flash ADC is simulated with tanner suit 180nm CMOS process with 1-V supply voltage and consumes 0.378mW. At 50 MS/s, high speed flash ADC has the effective number of bits of 5.97-bit and the figure of merit of 0.12 pJ/conversion-step, signal to noise distortion ratio is 37.74 db and SFDR is 46.7 db.

Keywords: ADC, Multiplexers, comparator, Preamplifiers, Ladder Network and Buffer

How to Cite?: Rana Vikram Pratap Singh Yadav, Neelam Srivastava, "Implementation of High Speed Flash ADC Using Multiplexer with Reduced Number of Preamplifier and Comparator Count", Volume 7 Issue 10, October 2018, International Journal of Science and Research (IJSR), Pages: 698-702, https://www.ijsr.net/getabstract.php?paperid=ART20191945, DOI: https://dx.doi.org/10.21275/ART20191945

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