International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064

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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 7 Issue 5, May 2018

Design and Implementation of a PLL using a Single-Event-Transient Hardened-by-Design (SETHBD) Charge Pump

Pallavi. K. R | Dr. K. N. Muralidhara

Abstract: The Phase Locked Loop (PLL) is a combined system of phase frequency detector (PFD), charge pump (CP), low pass filter (LPF), voltage controlled oscillator (VCO), frequency divider (FD). The PLL is widely used in RF and wireless transceivers, optical fiber receivers and carrier synthesis in cellular telephones etc. The PLL tracks the frequency changes of the input signal. Thus, a PLL goes through three stages- free running, capture and locked or tracking. Once the PLL is locked, it can track frequency changes in the incoming signals. In the proposed PLL, the designed PFD is free from dead zone. The single-event-transient hardened-by-design (SET-HBD) charge pump is used instead of traditional CP to overcome the single event effects (SEEs) such as single-event upset (SEU), multiple bit upset, single-event transient (SET), and latch up problems. Here we use the radiation hardened circuit and reference circuit along with the charge pump circuit. And the 5-stage current starved voltage controlled oscillator is used. And the divided by 4 frequency divider circuit is designed for feedback circuit using a 2-D flip-flops (N/4). The PLL design is implemented in cadence virtuoso 180nm technology with a supply voltage of 1.8V operates at a frequency of 1GHZ and all the simulations are done using cadence simulator.


Edition: Volume 7 Issue 5, May 2018,

Pages: 727 - 732

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