Design and Implementation of 16 X 16 High speed Vedic multiplier using Brent Kung Adder

Nidhi Singh, Mohit Singh

Abstract: In VLSI design, the performance of any system is determined by the performance of the elements i. e. Multiplier. Multiplier is the slow element in the system. The speed of multiplier depends on multiplication technique and type of adder. This paper proposes the architecture of 16 x 16 high speed binary arithmetic multiplier using Urdhva Tiryagbhyam sutra of Vedic mathematics. Urdhva Tiryagbhyam sutra is used for generating the partial products. The partial product addition in Vedic multiplier is realized using Brent Kung adder. The HDL used for design is Verilog and code is implemented in Xilinx ISE 14.7 software. The combinational path delay of 16x16 bit Vedic multiplier obtained after synthesis is compared with Vedic multiplier using MUX based adder and found that the proposed Vedic multiplier circuit seems to have better performance in terms of speed.

Keywords: Vedic Multiplier, Delay, VLSI, Brent Kung adder, Urdhva Tiryagbhyam Sutra, Verilog HDL

How to Cite?: Nidhi Singh, Mohit Singh, "Design and Implementation of 16 X 16 High speed Vedic multiplier using Brent Kung Adder", Volume 5 Issue 12, December 2016, International Journal of Science and Research (IJSR), Pages: 239-242, https://www.ijsr.net/getabstract.php?paperid=ART20163395, DOI: https://dx.doi.org/10.21275/ART20163395

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